This invention relates to testing semiconductor devices formed on a wafer. More particularly, the present invention relates to a new and improved method and apparatus for placing power and signal probes on a semiconductor die cut from the wafer and applying power and signals to the die while performing testing and failure analysis.
Failure analysis of a semiconductor device is done with a variety of techniques used to locate, analyze, and identify faults in the device. The semiconductor integrated circuit (IC) or chip is typically formed on a silicon substrate using a layering technique which results in a multilayered device composed of various layers of metal, polysilicon, dielectric and other materials. Many ICs are fabricated at once on a wafer. Thereafter, using one type of testing and failure analysis technique, the wafer is cut into die with each die or chip containing an IC. Testing or failure analysis is then performed on the die. If the IC is meets the functional specifications, the die is placed into a package and leads are attached between bond pads of the IC and bond pads of the package.
Typical failure analysis techniques used on the front side of the die include mechanical probing, electron beam probing, photo emission microscopy, and optical beam induced current (xe2x80x9cOBICxe2x80x9d). The die is placed on the platen of a testing station and power and signal probes are placed on the front surface of the die to power up the IC. The failure analysis techniques are then used on the front surface of the die to detect and isolate faults in the IC. Some optical failure analysis techniques, such as emission microscopy and OBIC, are also performed on the back side of the die.
Photo emission microscopy is a xe2x80x9chot spotxe2x80x9d detection technique which detects photons emitted from faults in the IC. The type of faults which typically generate a photo emission include junction defects, contact spiking, hot electrons, latch-up, poly filaments, and substrate damage and contamination. The photo emissions are typically the result of electron-hole recombinations which generate light primarily in the infrared region of the light spectrum. The photo emissions are transmitted through semi-transparent dielectric layers, polysilicon layers, and passivity layers, and emerge from the front side of the die where they may be seen by viewing the front side of the die. The photo emissions are also transmitted through the substrate of the die and emerge from the back side of the die where they may be seen by viewing the back surface of the die.
In photo emission microscopy, an infrared optical microscopic device or other infrared optical viewing device, such as a charge coupled device (CCD) camera with a monitor, is used to obtain an image of the photo emissions from the back side of the die. The photo emission image is overlaid on a bright field reference image of the IC to isolate and identify the fault sites associated with the photo emissions. Power and signals must be supplied to the IC in the photo emission microscopy technique. The power and signals are supplied to the IC by placing power and signal probes on the die and supplying power and signals from external sources to the probes when performing the testing or failure analysis.
The effectiveness of optical failure analysis techniques used on the front side of the die is diminished because of the increased complexity of many ICs. In particular, ICs are being manufactured with additional metal interconnect layers. The increasing number of layers makes photo emission microscopy from the front side of the die difficult, if not impossible, because of the lack of visibility of the photo emissions from the front side of the die. The additional metal interconnect layers include as many as six upper layers for power busses, high density signal routing signal lines, and bond pads. The metal interconnect layers are place above the substrate of the wafer where active devices, such as transistors, are formed. Active transistors are generally the source of most faults detectable using optical failure analysis techniques on the front side of the die. The photons emitted from the fault cannot pass through the numerous opaque metal interconnect layers of the device. Instead, the photon emissions pass between or are scattered around the metal interconnect layers, preventing the detection of photo emissions from the surface of the die or otherwise decreasing the accuracy of locating the fault. The effectiveness of the optical failure analysis techniques used on the front side of the die is diminished because the additional metal interconnect layers obstruct the visibility of faults in the active devices. However, optical photo emission microscopy can be effectively used on the back side of the die where it is less likely that faults are obstructed by metal interconnect layers.
If the IC on the die is found to be functional, the die is placed into the package for further testing. Typically, wire bonding is then used to directly connect bond pads of the die to bond pads of the package. Alternatively, tape-automated bonding is used to connect the bond pads of the die to bond pads of a tape bond which form the bond pads of the package. The bond pads of the tape bond are connected to pins of the package with leads to complete an electrical connection between the bond pads of the die and the pins of the package. The packaged IC is then tested for functionality and electrical specifications.
In tape-automated bonding, interconnections to connect the IC to the bond pads of the tape bond are patterned on a polymer tape. The interconnections are typically metal tracks or conductors on the tape to contact bond pads on the periphery of the die. The tape bond is attached to the bare die by contacting the bond pads to the metal tracks or the metal bumps. An adhesive is used to secure the tape bond to the die.
Application of the testing and failure analysis techniques on the back side of the die is complicated with existing die probing techniques. Typically, the die is affixed to a transparent support beneath an emission microscope or an infrared sensitive CCD camera. Power and signal probes are then placed on the contact pads of the semiconductor device after the die is inverted. The process of contacting the probes to the semiconductor device typically involves viewing the surface of the inverted die on a video monitor while mechanically manipulating the probes to place probes tips on the contact pads of the IC on the die. This process is complicated in terms of eye-to-hand coordination since the video image is a reverse image of the die from the viewpoint of a normal viewing. Also, the equipment operator must view the die surface indirectly though the video monitor rather than viewing the die surface directly while placing the probes on the die. The process of connecting the probes to the semiconductor device is tedious, time-consuming and prone to error.
Application of the testing and failure analysis techniques on the front side of the die is also complicated with existing probing techniques. The probes are typically placed on the front side of the die by contacting tips of the probes to the very small contact pads on the front side of the die by using a microscope. The probes have a relatively long, cantilevered-like arm which extend from micrometer-like devices used to adjust the mechanical position of the tips of the probes. Because of the relatively long arm of the probes and their cantilevered extension from the adjustment mechanism, the movement of the tip of the probes is magnified, which makes it difficult, tedious and time-consuming to precisely and accurately position the probe tip on the desired contact pad of the IC. Moreover, the probe tip is also subject to natural environmental vibrations because of the magnification effect of the relatively long arm of the probe. Consequently, connecting the probes to the semiconductor device for front side failure analysis techniques is also difficult and prone to error.
It is with respect to these and other considerations that have given rise to the present invention.
One aspect of the present invention relates to facilitating the application of probes to an IC on a die for testing and failure analysis. Other aspects of the invention relate to avoiding the difficulties and reducing the time required to connect the power and signal probes to the IC, avoiding reverse images and indirect viewing of the die while manipulating the probes, and avoiding the necessity for direct mechanical placement of the probes on the die.
In accordance with these features, one aspect of the present invention relates to a method of a performing testing or failure analysis on a die having bond pads connected to an integrated circuit formed on the die. The method involves electrically contacting an interconnector to the bond pad, extending the interconnector to a position beyond an exterior peripheral edge of the die while maintaining the electrical contact of the interconnector to the bond pad, and connecting a testing or analysis probe to the interconnector at a location beyond the exterior peripheral edge of the die, and supplying an electrical signal or electrical power through the probe to the interconnector and the bond pad and the integrated circuit, and performing the testing or failure analysis while supplying the signal or power to the integrated circuit. Preferably, the interconnector is adhesively connected to the die.
Another aspect of the present invention relates to the interconnector which electrically connects the probe to the bond pad of the die which contains the integrated circuit. The interconnector includes a piece of electrically insulating material having a front surface, an electrically conductive bump contact mounted on the front surface of the insulating material, an electrically conductive probe pad mounted on the front surface of the insulating material at a position spaced from the bump contact to be positioned beyond the peripheral edge of the die for contact with the probe, and an adhesive for physically holding the bump contact in electrical contact with the bond pad.
The strip or pad may be formed as a multi-layered laminated structure with a top insulating layer from which the bump contact extends and a conductive layer which defines the electrical conductor extending between the bump contact and the probe pad. Additional alternating layers of insulation and conductive material may be included in the laminated structure. A plurality of bump contacts may be located at a generally interior position of the pad, and a plurality of probe pads may be located at a generally exterior position of the pad adjacent to edges of the pad, thereby establishing multiple electrical contacts to multiple bond pads of the die from multiple probes.
Other preferable aspects of the method include connecting the interconnector to the die while a front side of the die is facing upward and inverting the die and the connected interconnector to face the front side of the die downward when performing the testing or failure analysis, preferably through a microscope.